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Condor Currents

Condor Computing

Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community. Brought to you by Condor Computing, high-performance RISC-V processor IP from Andes Technology.

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Episodes 39

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  • August 8 · length unknown

    Heterogeneous LLM Serving with General-Purpose Processing-Near-Memory for Retrieval-Based Sparse Attention

    ## Episode Summary In this episode, we cover: - **Heterogeneous LLM Serving with General-Purpose Processing-Near-Memory for Retrieval-Based Sparse Attention** (arXiv) - **Celty: SpMspV GPU Kernel and SIMT Co-Design for Efficient Dual-Sparse LLM Inference** (arXiv) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - notebookcheck.net** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • August 7 · length unknown

    PLoRA: An NDP-Enhanced Pooled-Memory System for Cost-Efficient Multi-LoRA Serving

    ## Episode Summary In this episode, we cover: - **PLoRA: An NDP-Enhanced Pooled-Memory System for Cost-Efficient Multi-LoRA Serving** (arXiv) - **Breaking Memory Bottlenecks in Quantum Control Systems for More Precise Experiments and Higher Throughput Computing** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - phoronix.com** (google_riscv) - **Performance aware shared memory hierarchy model for multicore processors - nature.com** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • August 6 · length unknown

    Architectural Implications of Agentic AI Workflows

    ## Episode Summary In this episode, we cover: - **Architectural Implications of Agentic AI Workflows** (arXiv) - **On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policies** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch) - **AMD Zen 6 CPU architecture may include new optimisations to tackle game stutter - kitguru.net** (google_arch) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • August 5 · length unknown

    LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension

    ## Episode Summary In this episode, we cover: - **LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension** (arXiv) - **A Time-Multiplexed Spiking Neural Network Accelerator with Pipelined Readout for FPGA Inference** (arXiv) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • August 4 · length unknown

    Themis: Software-Defined Hardware Prefetching

    ## Episode Summary In this episode, we cover: - **Themis: Software-Defined Hardware Prefetching** (arXiv) - **Beyond Static Policies: Dynamic Selection Among Modern Microarchitectural Policies** (arXiv) - **AMD Zen 6 CPU architecture may include new optimisations to tackle game stutter - KitGuru** (google_arch) - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • August 3 · length unknown

    Selective KV Cache Protection for Noise-Resilient LLM Inference on Analog Compute-In-Memory Systems

    ## Episode Summary In this episode, we cover: - **Selective KV Cache Protection for Noise-Resilient LLM Inference on Analog Compute-In-Memory Systems** (arXiv) - **WitCert: Sound Runtime Risk Observability and Gating for KV-Cache Quantization** (arXiv) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC) - Semiconductor Engineering** (google_riscv) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - cnx-software.com** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • August 2 · length unknown

    Windowed-MTP: Removing the Full-Context Draft-KV Tax at Million-Token Context

    ## Episode Summary In this episode, we cover: - **Windowed-MTP: Removing the Full-Context Draft-KV Tax at Million-Token Context** (arXiv) - **A Heterogeneous Neural Network Accelerator for End-to-End Multitask RF Signal Recognition** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - techpowerup.com** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • August 1 · length unknown

    A Photonic-CXL Memory Appliance for Scalable KV Cache Management in LLM Inference

    ## Episode Summary In this episode, we cover: - **A Photonic-CXL Memory Appliance for Scalable KV Cache Management in LLM Inference** (arXiv) - **SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow** (arXiv) - **RISC-V Targets Data Centers as Open ISA Pushes Beyond Embedded Systems - eetasia.com** (google_riscv) - **Openchip unveils BER10 RISC-V processor as Europe pursues greater digital sovereignty - New Electronics** (google_riscv) - **AI is stress-testing processor architectures and RISC-V fits the moment - EDN - Voice of the Engineer** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • July 31 · length unknown

    PIMID: A Full-System Simulator with Intricacy and Diversity for Processing-in-Memory

    ## Episode Summary In this episode, we cover: - **PIMID: A Full-System Simulator with Intricacy and Diversity for Processing-in-Memory** (arXiv) - **Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - electropages.com** (google_arch) - **Using a Performance Model to Implement a Superscalar CVA6** (riscv_news) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • July 30 · length unknown

    Investigating reservoir computing for branch predictionin pipelined processors using emerging CMOS memristor devices

    ## Episode Summary In this episode, we cover: - **Investigating reservoir computing for branch predictionin pipelined processors using emerging CMOS memristor devices** (arXiv) - **PortLBM: A Portable Lattice Boltzmann Tool Leveraging SYCL on AMD, NVIDIA, and Intel GPUs** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - design-reuse.com** (google_arch) - **RISC-V Targets Data Centers as Open ISA Pushes Beyond Embedded Systems - EE Times Asia** (google_riscv) - **RISC-V Targets Data Centers as Open ISA Pushes Beyond Embedded Systems - EE Times Asia** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • July 29 · length unknown

    SpecBox: Speculative Sandbox Scheduling for Efficient LLM Agent Serving

    ## Episode Summary In this episode, we cover: - **SpecBox: Speculative Sandbox Scheduling for Efficient LLM Agent Serving** (arXiv) - **Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching** (arXiv) - **Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SW** (riscv_news) - **A requiem for Optane, Intel's KV cache killer that could have eased the RAM price crunch** (the_register) - **Espressif begins mass production of ESP32-S31 wireless RISC-V SoC - LinuxGizmos.com** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • July 28 · length unknown

    SpacemiT MUSE Pi Pro is an octa-core RISC-V SBC with Armbian support - LinuxGizmos.com

    ## Episode Summary In this episode, we cover: - **SpacemiT MUSE Pi Pro is an octa-core RISC-V SBC with Armbian support - LinuxGizmos.com** (google_riscv) - **Modder builds 8,192-core GPU at home out of RISC-V microcontrollers — full "graphics card" draws over 2,000 watts of power, requires a 3D printer to program - Tom's Hardware** (google_riscv) - **Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU - Adafruit** (google_riscv) - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv) - **The next RISC-V processor frontier: AI - EDN - Voice of the Engineer** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • July 27 · length unknown

    TileSight: A First-Principles Tile-Centric Analytical GPU Performance Model from Cores to Clusters

    ## Episode Summary In this episode, we cover: - **TileSight: A First-Principles Tile-Centric Analytical GPU Performance Model from Cores to Clusters** (arXiv) - **Black-Box Performance Evaluation of Elastic Block Storage: Contract, Rate-Limiting Model, and Software Exploration** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - AOL.com** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - TechPowerUp** (google_riscv) - **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • July 26 · length unknown

    DGNA: Dissecting GPU NUMA Architecture through Microbenchmarking and Data Analysis

    ## Episode Summary In this episode, we cover: - **DGNA: Dissecting GPU NUMA Architecture through Microbenchmarking and Data Analysis** (arXiv) - **Isolation Failure From Shared Storage: Characterizing and Exploiting Page-Cache SCA Leakage Across Containers and VMs** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv) --- *Sponsored by AIEDA, Ago Consulting, and Zen Semiconductor*

  • July 25 · length unknown

    RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse

    ## Episode Summary In this episode, we cover: - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **AMD Zen 7 “2028” and Zen 8 “2030” CPU Architectures Confirmed – EPYC Florence “Zen 7” To Feature Next-Gen Node, & ACE Extensions - Wccftech** (google_arch) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) --- *Sponsored by LimitLess AI*

  • July 24 · length unknown

    AMD reveals CPU architecture roadmap through 2028, following Zen 6 'Venice' launch — Zen 7 'Florence' to de... - Yahoo Tech

    ## Episode Summary In this episode, we cover: - **AMD reveals CPU architecture roadmap through 2028, following Zen 6 'Venice' launch — Zen 7 'Florence' to de... - Yahoo Tech** (google_arch) - **AMD Zen 7 “2028” and Zen 8 “2030” CPU Architectures Confirmed – EPYC Florence “Zen 7” To Feature Next-Gen Node, DDR6 Memory & ACE Extensions - Wccftech** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **Armaan Gomes and Friends Deliver Playable Doom on a Whole New Platform: A Custom RISC-V CPU - Hackster.io** (google_riscv) --- *Sponsored by LimitLess AI*

  • July 22 · length unknown

    NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist

    ## Episode Summary In this episode, we cover: - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_arch) - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors** (semiengineering) - **HW-based Methods to Dynamically Throttle AI Performance (Princeton University)** (semiengineering) - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors - Semiconductor Engineering** (google_riscv) - **Buet tapes out open-source 32-bit RISC-V processor 'Pragati v1' - The Business Standard** (google_riscv) --- *Sponsored by LimitLess AI*

  • July 21 · length unknown

    SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput

    ## Episode Summary In this episode, we cover: - **SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput** (arXiv) - **Inter-Set Correlation-Aware Replacement Policy for Energy Efficient RTM-based Caches** (arXiv) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) --- *Sponsored by LimitLess AI*

  • July 20 · length unknown

    DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction

    ## Episode Summary In this episode, we cover: - **DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction** (arXiv) - **StreamingQEC: Streaming Quantum Error Correction in Tightly Integrated Quantum-Classical Systems via Certified Recurrence** (arXiv) - **RISC-V Milk-V Jupiter 2 SBC Benchmarked: 60 TOPS NPU and SiFive K3 SoC - Geeky Gadgets** (google_riscv) - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) --- *Sponsored by LimitLess AI*

Showing 21–39 of 39 episodes