Condor Currents

Condor Computing

Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community. Brought to you by Condor Computing, high-performance RISC-V processor IP from Andes Technology.

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Thursday · length unknown
MCF: A Memory- and Communication-Aware Co-Designed Framework for Long-Context LLM Inference
## Episode Summary In this episode, we cover: - **MCF: A Memory- and Communication-Aware Co-Designed Framework for Long-Context LLM Inference** (arXiv) - **Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Wednesday · length unknown
DeepInfer-Mac: Running a 750B-Class MoE on a 24 GB Laptop
## Episode Summary In this episode, we cover: - **DeepInfer-Mac: Running a 750B-Class MoE on a 24 GB Laptop** (arXiv) - **SPARTA: A Sparse Ternary LLM Accelerator with Adaptive Attention and Unified Datapath for Long-Context Edge Inference** (arXiv) - **As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - The Register** (google_riscv) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) - **New RISC-V microprocessor can run CPU, GPU, and NPU workloads simultaneously - Tom's Hardware** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Tuesday · length unknown
Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads
## Episode Summary In this episode, we cover: - **Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads** (arXiv) - **PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto Search** (arXiv) - **Ultra-Low-Latency IPC: RISCVLinux Part 3 - Hackster.io** (google_riscv) - **For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice** (riscv_news) - **SiFive makes the case for RISC-V as the control layer for custom AI accelerators - Jon Peddie** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Monday · length unknown
Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads
## Episode Summary In this episode, we cover: - **Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads** (arXiv) - **HAWK: Heterogeneity-Aware KV Cache Transfer for Efficient GPU-NPU Phase-Disaggregated LLM Inference** (arXiv) - **Efinix Sapphire RV64 SoC – Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs - CNX Software** (google_riscv) - **Efinix Goes 64-Bit with Its Latest Sapphire SoC FPGA Cores, Based on the RISC-V Architecture - Hackster.io** (google_riscv) - **RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 - Phoronix** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 25 · length unknown
panvram: GPU-resident random access to a human pangenome cohort
## Episode Summary In this episode, we cover: - **panvram: GPU-resident random access to a human pangenome cohort** (arXiv) - **BS-Spec: BFP-Based Bit-Sharing for Self-Speculative LLM Decoding with LUT-Driven Mixed-Precision Acceleration** (arXiv) - **Nuvia Architects’ New CPU Core Can Use Arm, RISC-V or x86 - HWCooling.net** (google_riscv) - **Lanxin Computing Unveils RISC-V Supernode Built on Its 48-Core LX500 Inference Chip - Pandaily** (google_riscv) - **Upbeat Technology’s Bluemag Pi Pairs RISC-V Processors and AI Inference for Advanced Flight Control - Embedded Computing Design** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 24 · length unknown
Proba: A High-Performance, Low-Traffic Probabilistic Spatial Memory Streaming Prefetcher
## Episode Summary In this episode, we cover: - **Proba: A High-Performance, Low-Traffic Probabilistic Spatial Memory Streaming Prefetcher** (arXiv) - **Stop Paying by the Letter: Accelerating Full-Chip RTL Simulation with Host-Side Tokenized Logging** (arXiv) - **UltraRISC Shows UR-CP400 RISC-V Core IP: RVA23, 8-Wide Out-of-Order, Delivery in Q1 2027 - Pandaily** (google_riscv) - **SpacemiT Pairs V100 RISC-V Server CPU With Three Servers, Kunlunxin M100 Validation and Linux - Pandaily** (google_riscv) - **RISC-V data center processors: server requirements - NeoTeo** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 23 · length unknown
SnakeCharmer: Orchestrating Utility, Timeliness, and Placement in GPU Prefetching
## Episode Summary In this episode, we cover: - **SnakeCharmer: Orchestrating Utility, Timeliness, and Placement in GPU Prefetching** (arXiv) - **Reorienting the Vector Axis: Restructuring FlashAttention for Long-Vector Processors** (arXiv) - **Chinese chipmakers roll out new RISC-V server CPUs for AI demand - Global Times** (google_riscv) - **DAMO Academy's XuanTie E908A Is an Automotive RISC-V CPU IP Aimed at ASIL-B and ASIL-D Designs - Pandaily** (google_riscv) - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - Nature** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 22 · length unknown
HAWK: Heterogeneity-Aware KV Cache Transfer for Efficient GPU-NPU Phase-Disaggregated LLM Inference
## Episode Summary In this episode, we cover: - **HAWK: Heterogeneity-Aware KV Cache Transfer for Efficient GPU-NPU Phase-Disaggregated LLM Inference** (arXiv) - **Accelerating CPU Speculative Decoding via Unified Graph Execution and Transactional KV Isolation** (arXiv) - **Why Chip Design AI Benchmarks Must Go Beyond Functional Correctness** (eetimes) - **SpacemiT V100: New RISC-V Server Processor Combines 46 Cores, DDR5 and PCIe 5.0 - igor´sLAB** (google_riscv) - **Alibaba unveils automotive RISC-V processor IP and roadmap for self-driving and robotics - TechNode** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 21 · length unknown
PAGE404: Breaking GPU Isolation Through Hardware-assisted Page Migration
## Episode Summary In this episode, we cover: - **PAGE404: Breaking GPU Isolation Through Hardware-assisted Page Migration** (arXiv) - **MemLLM: End-to-end In-Storage Acceleration of On-device Retrieval-Augmented Generation using Precomputed KV Caches** (arXiv) - **Linux 7.2-rc2 Raising The Default RISC-V 64-bit CPU Limit To 256 Cores - Phoronix** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - TechPowerUp** (google_riscv) - **SoCMake: Modular RISC-V SoCs for Radiation-Harsh and Safety-Critical Environments** (riscv_news) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 20 · length unknown
HBFSim: A Simulator for Exploring HBF in Memory Hierarchies for LLMs
## Episode Summary In this episode, we cover: - **HBFSim: A Simulator for Exploring HBF in Memory Hierarchies for LLMs** (arXiv) - **A Hybrid GPU and Processing-Near-Memory Architecture with Shared DRAM for Efficient Prefill-Decode Disaggregation** (arXiv) - **RISC-V extensions for high performance embedded computing ... - eeNews Europe** (google_riscv) - **Server-class 46-core RISC-V CPU runs mainstream Linux - LinuxGizmos.com** (google_riscv) - **SpacemiT V100 processor: 46-core RISC-V server - NeoTeo** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 19 · length unknown
Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday
## Episode Summary In this episode, we cover: - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Nvidia Vera CPU Architecture: Max single-threaded CPU at scale for agents - GamesBeat** (google_arch) - **SpacemiT Announces The V100 Server-Class RISC-V Processor - Phoronix** (google_riscv) - **RISC-V Soft Cores Go 64-Bit With Efinix Sapphire RV64 - The Futurum Group** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 18 · length unknown
FORGE: Procedural Weight Generation for Sparse MoE Inference
## Episode Summary In this episode, we cover: - **FORGE: Procedural Weight Generation for Sparse MoE Inference** (arXiv) - **AlignPred: Error-Controlled KV Cache Compression via Alignment and Predictive Coding** (arXiv) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU - alphaXiv** (google_riscv) - **Efinix Announces New Sapphire RV64 SoC, Bringing 64-Bit RISC-V Performance to Embedded FPGA Designs - Embedded Computing Design** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 17 · length unknown
Foundations of Hardware-Software Leakage Contracts
## Episode Summary In this episode, we cover: - **Foundations of Hardware-Software Leakage Contracts** (arXiv) - **PAGE404: Breaking GPU Isolation Through Hardware-assisted Page Migration** (arXiv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) - **RISC-V Soft Processor System on DE10-Lite - Hackster.io** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 16 · length unknown
Top-Down Microarchitecture Analysis Without Causal Modelling Is Dangerous!
## Episode Summary In this episode, we cover: - **Top-Down Microarchitecture Analysis Without Causal Modelling Is Dangerous!** (arXiv) - **Minimum RISC-V: Maximum FPGA Efficiency** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 15 · length unknown
TALU: A Reconfigurable Tiled-ALU Grid for RISC-V
## Episode Summary In this episode, we cover: - **TALU: A Reconfigurable Tiled-ALU Grid for RISC-V** (arXiv) - **CacheSmith: Accurate RAG Serving under Latency SLOs with Adaptive KV Reuse** (arXiv) - **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - Wccftech** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **Meta’s Muse AI Agent Just Designed A Crypto-Specific SoC On The RISC-V Architecture For $2,000 To Transform The Thru Blockchain Into “The Fastest On Earth” - Wccftech** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 14 · length unknown
Programmable Data Layouts via On-The-Fly Data Transformation
## Episode Summary In this episode, we cover: - **Programmable Data Layouts via On-The-Fly Data Transformation** (arXiv) - **Simulate Before You Scale: High-Fidelity LLM Inference Planning Without GPUs** (arXiv) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 13 · length unknown
Read What Matters: Query-Adaptive Quantization for KV Caches
## Episode Summary In this episode, we cover: - **Read What Matters: Query-Adaptive Quantization for KV Caches** (arXiv) - **A Pipelined FPGA Architecture for Banded Sparse Matrix Dense Matrix Multiplication in Longformer** (arXiv) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 12 · length unknown
CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support
## Episode Summary In this episode, we cover: - **CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support** (arXiv) - **Taking Tokenization off the Host for Agentic LLM Serving** (arXiv) - **For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice** (riscv_news) - **What Is a Microarchitecture? Understanding Processors and Register Files in an ARM Core - All About Circuits** (google_arch) - **Armaan Gomes and Friends Deliver Playable Doom on a Whole New Platform: A Custom RISC-V CPU - Hackster.io** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 11 · length unknown
A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
## Episode Summary In this episode, we cover: - **A Framework for Accelerating Transformer Inference on RISC-V for Edge AI** (arXiv) - **ECO: Energy-Oriented Configuration Optimization for Attention FFN Disaggregated LLM Serving** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch) - **Efinix Goes 64-Bit with Its Latest Sapphire SoC FPGA Cores, Based on the RISC-V Architecture - Hackster.io** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 10 · length unknown
SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS
## Episode Summary In this episode, we cover: - **SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS** (arXiv) - **BenchmarkAnything: Agent-Driven Construction of Simulator-Ready Microarchitecture Benchmarks** (arXiv) - **Nuvia Architects’ New CPU Core Can Use Arm, RISC-V or x86 - HWCooling.net** (google_riscv) - **Upbeat Technology’s Bluemag Pi Pairs RISC-V Processors and AI Inference for Advanced Flight Control - Embedded Computing Design** (google_riscv) - **Efinix® Brings 64-Bit RISC-V Performance to Embedded FPGA Designs With New Sapphire™ RV64 SoC - Yahoo Finance** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

Showing 1–20 of 93 episodes