EUV The Focal Point

EUV The Focal Point - Team

EUV The Focal Point is your Extreme Ultraviolet (EUV) lithography podcast.

Industry Briefings:
Cover leading-edge nodes, DRAM, HBM and strategy moves from ASML & co. and from the end customers Apple & co.

Focus Deep Dives:
Unpack physics, plasma, optics and how EUV scanners really work.

Hosted by EUV experts Samantha and Jack, built entirely with AI (a technology that itself relies on EUV-made chips ;-) using company newsrooms, Wikipedia and news sites.

AI can make mistakes: always verify the information independently before using it as a basis for business decisions.

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S1 · E59
Thursday · 16 min
[059] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week is less about a new EUV scanner milestone and more about the economics that determine when lithography capacity becomes valuable. Intel connects 18A-P to Diamond Rapids, Samsung and SMIC show renewed foundry pricing power, and Chinese memory investment continues to scale. Key takeaways: - Intel presented Diamond Rapids at Hot Chips 2026 and tied the product to Intel 18A-P and Foveros Direct 3D packaging. - The Hot Chips update partially answers an earlier podcast outlook asking whether Intel 18A-P risk production would become concrete product activity. - TrendForce reported that Intel may use TSMC N2X for some Razor Lake compute dies in 2027, but the sourcing plan remains unconfirmed. - Reuters reported Samsung raised prices for some new foundry orders by up to 15%, with its SF4 line at Pyeongtaek running at full capacity. - Samsung’s price increases are an indirect EUV signal because high utilization improves the economics of installed advanced-node lithography capacity. - SMIC reported second-quarter revenue above $3 billion, wafer shipments up 14% sequentially, average selling prices up 5.7%, and utilization at 93.7%. - YMTC’s parent plans a roughly RMB 33 billion Shanghai IPO to fund production upgrades and advanced-storage R&D. - The week’s central theme is manufacturing optionality: Intel can push 18A-P while preserving TSMC options, and customers are paying more to secure scarce capacity. - No major new official ASML EUV shipment or High-NA production milestone was identified for this week. Glossary: Extreme Ultraviolet (EUV) — 13.5-nanometer lithography used for the most demanding layers in advanced logic and memory manufacturing. Intel 18A-P — Intel’s performance-enhanced extension of the Intel 18A process family. N2X — TSMC’s high-performance extension of its 2-nanometer process family, targeted at performance-sensitive applications. Foundry — A semiconductor manufacturer that fabricates chips designed by external customers. Utilization — The share of available manufacturing capacity actively being used. Average selling price (ASP) — Average revenue received per unit sold, such as a processed wafer. Foveros Direct 3D — Intel’s advanced 3D packaging technology for direct die-to-die integration. High Bandwidth Memory (HBM) — Stacked DRAM designed for very high bandwidth in AI and high-performance-computing systems. Deep Ultraviolet (DUV) — Older lithography technology still used across many semiconductor layers and in advanced production where EUV is unavailable or uneconomic.
S1 · E58
August 18 · 14 min
[058] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Samsung’s revised foundry roadmap puts High-NA EUV around the 1-nanometer-class generation in 2030 while extending the life of its Low-NA EUV platform. At the same time, record equipment spending, new equity financing, and packaging investments show that the economic race is increasingly about sequencing capital across the whole manufacturing system rather than adopting one tool first. Key takeaways - Samsung reportedly moved SF1.4 from a 2027 target to 2029 and plans High-NA EUV insertion with its 1-nanometer-class process around 2030. - Samsung’s roadmap implies continued Low-NA EUV use for SF1.4+ while the company concentrates near-term resources on the SF2 family. - Applied Materials reported record fiscal Q3 2026 revenue of $9.12 billion, up 25% year over year, and guided fiscal Q4 revenue to about $10.25 billion, plus or minus $500 million. - Applied Materials raised its calendar-2026 advanced-packaging growth expectation to more than 70%, reinforcing the broader process-equipment signal highlighted in the August 4 outlook. - Intel upsized its common-stock offering from $15 billion to $20 billion and expects approximately $19.7 billion of net proceeds; the company says proceeds may include capital expenditures and working capital. - TSMC approved about $29.44 billion of capital appropriations covering advanced technology, advanced packaging, specialty capacity, fabs, and facility systems. - TSMC and Sony signed a definitive agreement for a next-generation image-sensor joint venture in Kumamoto, with volume production targeted for 2029. - SPIL reportedly broke ground on a nearly NT$100 billion Douliu plant that will add CoWoS capacity, with first-phase operations planned for 2028. - Nanya Technology says it is evaluating potential expansion sites but has not made a decision on reported new fabs in Yunlin and Pingtung. - U.S. policy pressure is increasingly reaching foundries themselves, with lawmakers pushing stricter scrutiny of advanced-chip orders that could indirectly serve sanctioned Chinese firms. Glossary Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light for critical patterning at advanced semiconductor nodes. High Numerical Aperture (High-NA) EUV — The newer EUV platform intended for tighter critical-layer patterning and selective future-node insertion. Low Numerical Aperture (Low-NA) EUV — The established 0.33-NA EUV platform used broadly in current advanced logic and memory production. SF2 — Samsung Foundry’s 2-nanometer-class process family. SF1.4 — Samsung Foundry’s 1.4-nanometer-class process generation, now reported for 2029. Intel 14A — Intel Foundry’s next-generation process platform planned after Intel 18A. CoWoS — Chip on Wafer on Substrate, an advanced packaging approach used for large AI accelerators and HBM integration. HBM — High Bandwidth Memory, stacked memory used with advanced AI and high-performance computing processors. DRAM — Dynamic Random-Access Memory, the volatile memory technology underlying mainstream memory products and HBM.
S1 · E57
August 14 · 26 min
[057] Deep Dive Topic - New Ways to Store Bits
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. EPISODE TEASER Why is the memory industry exploring RRAM, MRAM, and new DRAM concepts when SRAM, DRAM, and NAND already work so well? This episode explains the physical storage mechanisms, the engineering trade-offs, and the most realistic application paths. It also clarifies why “DRAM+” is an umbrella term rather than one standardized memory technology. KEY TAKEAWAYS - Every memory tier trades speed, density, energy, endurance, retention, cost, and integration complexity. - Conventional DRAM stores charge in a capacitor and must refresh it because the charge leaks away. - “DRAM+” can describe enhanced DRAM approaches such as HBM, gain-cell or capacitorless DRAM, three-dimensional integration, embedded DRAM, and processing near the memory. - RRAM stores information as resistance by moving ions or defects in a switching layer; variability is one of its central challenges. - STT-MRAM writes through a magnetic tunnel junction, while SOT-MRAM separates the read and write paths. - Nonvolatile memories reduce standby and refresh energy, but active write energy and peripheral circuits still matter. - RRAM and MRAM can support compute-in-memory, but array parasitics, data conversion, write control, and device variation limit idealized gains. - Advanced DRAM is the strongest near-term route for main memory; MRAM and RRAM are more likely to expand first in embedded and specialized roles. - The likely future is a more heterogeneous memory hierarchy, not one universal replacement. GLOSSARY DRAM — Dynamic random-access memory. Volatile memory that usually stores each bit as charge in a capacitor and requires periodic refresh. DRAM+ — A nonstandard umbrella term used here for enhanced DRAM cells, architectures, packaging, stacking, and processing-near-memory concepts. SRAM — Static random-access memory. Fast volatile memory commonly used for processor caches; a typical cell uses several transistors. NAND flash — Dense nonvolatile storage that retains data without power and is programmed and erased in larger groups than RAM. RRAM or ReRAM — Resistive random-access memory. Nonvolatile memory that stores data in different resistance states. MRAM — Magnetoresistive random-access memory. Nonvolatile memory that stores data in magnetic orientation and reads it through a resistance difference. STT-MRAM — Spin-transfer torque MRAM. A form of MRAM in which write current passes through the magnetic tunnel junction. SOT-MRAM — Spin-orbit torque MRAM. A form of MRAM with a separate lateral write path that acts on the magnetic free layer. Crossbar array — A grid of crossing conductors with a memory element at each intersection; useful for dense storage and parallel analog operations. Compute-in-memory — An architecture that performs selected operations in or very near memory arrays to reduce data movement.
S1 · E56
August 10 · 11 min
[056] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Nanya Technology has turned EUV memory expansion into a funded fab schedule, while TeraFab has gained a confirmed Texas site and an initial investment figure. AMD and TSMC provide fresh demand-side evidence, and reported Chinese-tool evaluations by Samsung and SK hynix show how export controls can reshape equipment qualification beyond lithography. Key takeaways - Nanya approved up to NT$346.6 billion of Fab 5A capital expenditure for 2026-2029, including EUV equipment. - Fab 5A is designed for 45,000 wafer starts per month, with first-phase capacity targeted at 35,900 WSPM. - Nanya plans wafer input in the second half of 2027, with 30,000 WSPM targeted for 2028 and 35,900 WSPM for 2029. - SpaceX and Tesla identified Grimes County, Texas, as the TeraFab site and announced an initial investment of $16.8 billion. - TeraFab still has no disclosed EUV scanner count, mask strategy, detailed process flow, or public production qualification schedule. - AMD reported Q2 2026 revenue of $11.5 billion; Data Center revenue was $6.7 billion, up 107% year over year. - TSMC reported July 2026 revenue of NT$467.58 billion, up 44.7% year over year. - Reuters reported evaluations of AMEC etch tools by Samsung and SK hynix, while both companies denied testing AMEC equipment for use in China and no broad deployment decision was reported. Glossary Extreme Ultraviolet (EUV) — Advanced lithography using 13.5-nanometer light for critical semiconductor patterning. Dynamic Random-Access Memory (DRAM) — Volatile memory used widely in servers, PCs, mobile devices, and AI systems. Wafer starts per month (WSPM) — A fab-capacity measure describing how many wafers enter production each month. 1C / 1D / 1E DRAM — Successive 10-nanometer-class DRAM process generations in Nanya’s roadmap. Capital expenditure (capex) — Spending on long-lived manufacturing assets such as fabs and production equipment. Etch — A semiconductor process that selectively removes material to transfer patterns into underlying layers. Mask strategy — The plan for photomasks and patterning steps used to manufacture a chip design. Process flow — The ordered sequence of fabrication steps used to build semiconductor devices.
S1 · E55
August 6 · 9 min
[055] Deep Dive Topic - Recap of H1 2026
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. In this H1 2026 review, EUV lithography is examined not as a single-machine breakthrough, but as the coordinating system behind AI-driven semiconductor manufacturing. The episode covers Low-NA productivity, the selective economic case for High-NA, rising HBM demand, advanced packaging, mask and metrology constraints, and the global expansion of leading-edge fabs. The central question is no longer who can print the smallest feature, but who can convert scarce tools, photons, engineering capacity, and cleanroom space into reliable compute at scale.
S1 · E54
August 4 · 20 min
[054] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks beyond the EUV scanner to the design and manufacturing tools that turn advanced patterns into profitable silicon. SK hynix’s HBM4 ramp, strong results from Lam Research and KLA, and certified Synopsys flows for Intel 14A all point to the same conclusion: process integration and yield control are becoming as strategic as exposure capacity. Key takeaways - SK hynix reported second-quarter revenue of 79.3 trillion won and operating profit of 60.5 trillion won. - SK hynix began mass shipments of HBM4 in the second quarter and plans to ramp production in the second half of 2026. - SK hynix has finalized long-term agreements with around 10 customers and is accelerating the M15X mass-production schedule. - Lam Research reported record quarterly revenue of 6.72 billion dollars and guided the September quarter to about 8.1 billion dollars, plus or minus 400 million dollars. - KLA reported quarterly revenue of 3.66 billion dollars and guided the September quarter to 4.0 billion dollars, plus or minus 200 million dollars. - Synopsys certified AI-powered EDA and multiphysics flows for Intel 14A, including support across silicon, packaging, thermal, power-integrity, and electromagnetic analysis. - High-NA EUV economics depend on the full manufacturing flow, including masks, resists, etch transfer, metrology, design rules, and packaging. - Reuters reported that China has begun producing domestically developed immersion DUV lithography systems, although high-volume reliability and performance remain unproven. - No new official EUV scanner shipment count was identified this week; the strongest signals came from the surrounding equipment and design ecosystem. Glossary Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light to pattern the most advanced semiconductor layers. High Numerical Aperture (High-NA) EUV — A higher-resolution EUV platform intended for selected critical layers at future advanced nodes. Deep Ultraviolet (DUV) — Lithography using longer-wavelength ultraviolet light; immersion DUV remains important across mature and advanced process flows. High Bandwidth Memory (HBM) — Vertically stacked memory designed to provide very high data bandwidth for AI and high-performance computing. Dynamic Random-Access Memory (DRAM) — Volatile working memory used in servers, computers, mobile devices, and HBM stacks. Electronic Design Automation (EDA) — Software used to design, verify, optimize, and prepare chips for manufacturing. Design Technology Co-Optimization (DTCO) — Joint optimization of chip design rules and process technology. Process control — Inspection, metrology, analytics, and feedback used to maintain yield and manufacturing stability. Multiphysics analysis — Combined modeling of electrical, thermal, mechanical, and electromagnetic effects in a chip and package.
S1 · E53
July 30 · 23 min
[053] Deep Dive Topic - Heterogeneous Integration: The Evolution of System Architecture
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Heterogeneous integration is changing how advanced semiconductor systems gain performance. This episode explains why shrinking transistors is no longer enough on its own, how chiplets and advanced packaging connect specialized logic, memory, input-output, photonics, and other functions, and why artificial intelligence is accelerating the transition. It also examines the technical, economic, and supply-chain trade-offs behind the trend. KEY TAKEAWAYS - Transistor scaling remains essential, but modern performance gains increasingly come from system-level integration. - Heterogeneous integration combines dies made for different functions, process nodes, and sometimes different materials. - Chiplets can improve yield, reuse, product flexibility, and development speed. - Die-to-die links introduce latency, power, protocol, packaging, and test overhead. - Interposers, silicon bridges, through-silicon vias, and hybrid bonding enable dense communication inside advanced packages. - High-bandwidth memory is a central driver because artificial intelligence and high-performance computing are often limited by data movement. - Thermal management, mechanical stress, package warpage, and final assembly yield are major constraints. - UCIe aims to create a more interoperable chiplet ecosystem, but physical and manufacturing compatibility remain difficult. - Advanced packaging increases the strategic importance of foundries, assembly and test providers, materials, equipment, metrology, and design software. - Lithography remains critical both for leading-edge chiplets and for fine-patterned package structures. GLOSSARY Chiplet: A die designed to operate as one building block inside a larger multi-die system. Heterogeneous integration: Combining different dies, process technologies, functions, or materials in one package or system. Interposer: An intermediate wiring layer that provides dense connections between dies and the package substrate. High-bandwidth memory: Vertically stacked dynamic random-access memory designed for very wide, energy-efficient links to nearby processors. Through-silicon via: A vertical electrical connection passing through a silicon die or wafer. Hybrid bonding: Fine-pitch die or wafer bonding that joins copper connections and surrounding dielectric surfaces without conventional solder bumps. Two-and-a-half-dimensional integration: Side-by-side dies connected through a dense interposer or bridge. Three-dimensional integration: Active dies stacked vertically and connected with dense vertical links. Known good die: A die tested before assembly to reduce the risk of placing a defective component into an expensive package. UCIe: Universal Chiplet Interconnect Express, an industry specification for die-to-die communication.
S1 · E52
July 27 · 19 min
[052] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode follows the shift from isolated chip orders toward integrated agreements covering logic, High Bandwidth Memory, packaging, optics, and data-center infrastructure. Samsung–Broadcom and NVIDIA–SK Group provide the demand signals, while ZEISS, Intel, and China’s memory makers show what the manufacturing system must deliver—and where its constraints remain. Key takeaways • Samsung and Broadcom signed an MOU estimated at more than $200 billion through 2030 across HBM, 2-nanometer-and-below foundry technology, and advanced packaging. • NVIDIA and SK Group announced a $500-billion-plus initiative that includes a 2-gigawatt AI factory and a long-term next-generation memory partnership. • SK Telecom plans the first facility in its NVIDIA Vera Rubin and SK hynix HBM4 buildout to come online in 2027. • ZEISS SMT is adding about 25,000 square meters of production and production-related space in Oberkochen, with High-NA EUV optics among the targeted technologies. • Reuters reported that planned CXMT fabs could lift capacity above 600,000 wafers per month, while restricted EUV access remains a major advanced-memory constraint. • CXMT shares rose 466 percent in their Shanghai debut after an $8.6 billion IPO. • Intel reported Q2 revenue of $16.1 billion; Intel Foundry revenue reached $5.8 billion, while the segment recorded an operating loss of about $2.1 billion. • No new industry-wide EUV scanner shipment total was disclosed this week; the demand signal is indirect and embedded in customer and supplier commitments. Glossary Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light for critical layers in advanced logic and memory. High Numerical Aperture (High-NA) EUV — A newer EUV platform with higher optical resolution than conventional Low-NA EUV. High Bandwidth Memory (HBM) — Stacked dynamic random-access memory designed for very high data throughput near accelerators. Dynamic Random-Access Memory (DRAM) — Volatile working memory used in servers, personal computers, and many electronic systems. Deep Ultraviolet (DUV) — Mature lithography using longer wavelengths than EUV, often requiring more patterning steps at advanced dimensions. Memorandum of Understanding (MOU) — A framework describing intended cooperation that may precede binding commercial contracts. Risk production — An early manufacturing phase used to validate process maturity before broader volume production. Advanced packaging — Technologies that integrate multiple logic, memory, and interconnect components into one high-performance system.
S1 · E51
July 21 · 11 min
[051] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. High-NA EUV infrastructure is moving from plans into physical installation as the first ASML EXE:5200 components reach Albany NanoTech. This episode examines why scanner power alone does not determine useful output: workforce retention, mask control, pellicle transmission, customer commitments, and research access increasingly shape EUV economics. Key takeaways - The first ASML TWINSCAN EXE:5200 components have begun arriving at Albany NanoTech, with first light targeted later in 2026 and research operations expected in early 2027. - Intel and Fortinet will collaborate on the Security Processor 6, but no process node, wafer volume, or EUV usage was disclosed. - ASML plans a €20,000 conditional retention grant for eligible employees who remain from 2027 through 2030. - Micron signed automotive Strategic Customer Agreements with seven major ecosystem partners to improve long-term supply, pricing, and technology visibility. - The 2026 EUVL and Source Workshop proceedings highlight rising mask-related variability, High-NA DRAM co-optimization, and higher-power EUV source development. - Lintec reports approximately 90% transmittance and up to 66-fold durability improvement for a carbon-nanotube pellicle under specified test conditions. - A 90%-transmitting pellicle leaves about 81% after two passes, while 95% leaves about 90%, illustrating why small transmission gains can materially affect dose and throughput. - This was a light week for new scanner shipment totals, and Intel’s manufacturing node for the Fortinet collaboration remains unclear. Glossary Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light to pattern advanced semiconductor layers. High Numerical Aperture (High-NA) EUV — A higher-resolution EUV platform using 0.55 numerical aperture optics. Low Numerical Aperture (Low-NA) EUV — The established 0.33 numerical aperture EUV platform used in high-volume manufacturing. Pellicle — A thin membrane that protects a photomask from particles while transmitting exposure light. Reticle — The reflective EUV photomask carrying the circuit pattern projected onto a wafer. Dynamic Random-Access Memory (DRAM) — Volatile memory used in computing systems and as the base technology for high-bandwidth memory. Application-Specific Integrated Circuit (ASIC) — A chip designed for a defined function rather than general-purpose computing. First light — The first successful generation and operation of EUV light in an installed scanner.
July 16 · 19 min
[050] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. High-NA EUV has moved into a shipping logic product, with Intel and ASML qualifying selected Panther Lake layers on the EXE platform. ASML also raised its 2026 outlook and outlined major Low-NA and DUV capacity increases, showing that the next lithography era will be based on coexistence rather than immediate replacement. Key takeaways: - Intel Foundry is shipping a subset of Panther Lake products with selected Intel 18A layers dual-qualified on High-NA EUV. - ASML says yields on the High-NA-qualified layers match its established NXE Low-NA platform. - Intel is using High-NA selectively rather than replacing the full Intel 18A lithography flow. - ASML reported Q2 net sales of €9.3 billion, a 54.0% gross margin, and €2.9 billion net income. - ASML raised its 2026 sales outlook to €43–45 billion. - ASML plans to increase its approximately 65-system 2026 Low-NA EUV capacity by 30% for 2027. - SK Hynix completed a $26.5 billion U.S. ADR offering intended partly for fabs and equipment including EUV scanners. - Micron’s Hiroshima expansion targets equipment installation from the second half of 2028 and supports future EUV-enabled DRAM and HBM capacity. - High-NA adoption is likely to remain layer-selective until its cost-per-good-layer advantage is proven across more products. Glossary: Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light for advanced semiconductor patterning. High Numerical Aperture (High-NA) EUV — ASML’s newer EUV platform with higher optical resolution than conventional EUV. Low-NA EUV — The established 0.33-NA EUV platform used in current high-volume logic and memory production. Intel 18A — Intel’s advanced process node used for Panther Lake processors. Dual qualification — Approval of two process or equipment routes to manufacture the same layer or product. NXE — ASML’s established Low-NA EUV scanner family. EXE — ASML’s High-NA EUV scanner family. American Depositary Receipt (ADR) — A U.S.-traded security representing shares in a foreign company. Dynamic Random-Access Memory (DRAM) — Volatile memory used as working memory in computing systems. High Bandwidth Memory (HBM) — Stacked DRAM optimized for very high data bandwidth in AI and high-performance computing.
S1 · E49
July 6 · 14 min
[049] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode is a light week for new EUV scanner shipment numbers, but a strong week for capacity signals. South Korea moved from capital pledges to execution pressure, Samsung and TSMC showed how roadmap credibility now depends on design ecosystem readiness, and IBM’s nanostack work sharpened the question of what High-NA EUV must prove before production insertion. Key takeaways - No new official ASML EUV shipment count or High-NA production insertion milestone surfaced this week. - South Korea’s president pushed officials to accelerate chip and AI projects, emphasizing permits, land, power, and water as capacity bottlenecks. - Reuters reported expected investments of about 400 trillion won each from Samsung and SK hynix in southwest chip sites, plus 81 trillion won for a Chungcheong packaging cluster. - SK hynix’s Cheongju plan points to 100 trillion won of investment, including 80 trillion won for M17 NAND and 20 trillion won for P&T7 advanced packaging and test. - Samsung reaffirmed SF1.4 volume production for 2029 and SF1.4+ for 2030, while highlighting DTCO as a major contributor to SF2-to-SF2P gains. - Anthropic’s reported exploratory talks with Samsung on 2nm and advanced packaging remain unconfirmed but show AI companies seeking foundry optionality. - Socionext plans a September 2026 tape-out of a compute chiplet on TSMC A14, making A14 ecosystem readiness more concrete. - Nvidia’s China AI chip position is under pressure from Huawei and local suppliers, while China remains blocked from ASML EUV systems. - IBM’s nanostack announcement is research, not production, but it reinforces the value of early High-NA EUV learning at Albany. - Reported TSMC price increases, Apple product-cost pressure, and Broadcom’s Apple deal all point to scarcity being converted into pricing power and long-term contracts. Glossary Extreme Ultraviolet (EUV) — 13.5-nanometer lithography used for critical layers in leading-edge semiconductor manufacturing. High Numerical Aperture (High-NA) EUV — ASML’s next-generation EUV platform with higher resolution and a more demanding process ecosystem. Low Numerical Aperture (Low-NA) EUV — The current mainstream EUV platform used in high-volume manufacturing. Design Technology Co-Optimization (DTCO) — Joint optimization of chip design rules and manufacturing processes to improve power, performance, area, and yield. High Bandwidth Memory (HBM) — Stacked DRAM used beside AI accelerators to deliver very high memory bandwidth. Dynamic Random-Access Memory (DRAM) — Volatile memory used in servers, PCs, phones, and HBM stacks. NAND — Non-volatile flash memory used for storage in devices and data centers. Tape-out — The point when a chip design is finalized and sent for manufacturing masks and fab processing. Advanced packaging — Integration technologies that connect logic, memory, and chiplets into high-performance systems. Option value — The strategic value of learning early so companies can choose among technologies before production decisions are locked.
S1 · E48
June 29 · 22 min
[048] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at EUV as part of a broader manufacturing system rather than a standalone scanner story. South Korea’s cluster plans, Micron’s record quarter, SK Hynix’s proposed U.S. listing, Dutch pushback on export controls, ASML’s photonics work with TNO, and xLight’s light-source ambitions all point to the same theme: future lithography capacity is being financed and managed like strategic infrastructure. Key takeaways: - South Korea is preparing a new southwest semiconductor hub, with local reports suggesting investments could exceed 1,000 trillion won over several years. - The expected South Korean support package is infrastructure-heavy: power, water, land, workforce training, transport, and housing all matter for EUV-ready capacity. - Micron reported record fiscal Q3 revenue of $41.46 billion and said data-center revenue exceeded $25 billion in the quarter. - Micron has signed 16 strategic customer agreements and expects memory tightness to persist beyond calendar 2027. - Micron projects fiscal 2026 capex of about $27 billion and expects higher quarterly capex in fiscal 2027, with construction capex driving more than half the year-over-year increase. - SK Hynix plans to raise up to 45.45 trillion won, or about $29.4 billion, through a U.S. American Depositary Receipt listing. - Dutch officials are pushing back against the MATCH Act because it could force allies into U.S.-style China export controls and affect DUV servicing. - ASML and TNO will use DUV and I-line lithography in a new Eindhoven pilot line for six-inch indium phosphide photonic chips. - The xLight $350 million fundraising item remains reported rather than officially announced; the official anchor is the June 2 U.S. CHIPS Act award. - This week’s focus is a mixed-fleet view of lithography: EUV carries the densest layers, but DUV still carries much of scale, yield, reliability, and cost. Glossary: Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light for the most critical layers in advanced logic and memory. High Numerical Aperture (High-NA) — Next-generation EUV optics with higher resolution potential, but higher cost and integration complexity. Deep Ultraviolet (DUV) — Lithography using longer wavelengths such as 193 nanometers and 248 nanometers, still essential for many advanced-node layers. Dynamic Random-Access Memory (DRAM) — Volatile memory used across servers, PCs, mobile devices, and high-bandwidth memory stacks. High Bandwidth Memory (HBM) — Stacked DRAM optimized for very high data bandwidth near AI accelerators and graphics processors. American Depositary Receipt (ADR) — A U.S.-traded certificate representing shares of a foreign company. Free-electron laser — A light source using accelerated electrons; xLight is developing this approach as an alternative EUV source. Indium phosphide (InP) — A compound semiconductor material used for active photonic functions such as lasers and modulators. Strategic customer agreement — A longer-term commercial agreement intended to improve supply visibility, pricing durability, or capacity commitment.
S1 · E47
June 22 · 16 min
[047] Industry briefing - EUV The Focal Point
Take the survey on Spotify! This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at EUV less as a scanner-capacity headline and more as a manufacturing translation engine. The focus is the new 300-millimeter 2D-material transistor work from imec, ASML, and TSMC, plus Intel’s 18A-P risk-production milestone, ASML’s denial of EUV shipments to China, and fresh HBM4E sampling pressure from SK hynix. Key takeaways: - imec, ASML, and TSMC demonstrated complementary 2D-material nFETs and pFETs on a 300-millimeter wafer at 50-nanometer contacted poly pitch. - The 2D-material result used single-patterning EUV and reported 94 percent operational transistors, moving the work closer to manufacturable process exploration. - Intel 18A-P entered risk production with claims of 9 percent higher performance at the same power or 18 percent lower power at the same performance versus Intel 18A. - Intel’s VLSI update also highlighted thermal, via-resistance, CFET, GaN-on-silicon, and ruthenium-interconnect research as part of a longer scaling stack. - ASML denied that it has ever shipped an EUV machine, or EUV-specific components or modules, to China. - SK hynix shipped samples of 12-layer HBM4E to major customers, claiming up to 16 gigabits per second per pin and more than 20 percent power-efficiency improvement. - Intel’s appointment of Seok-Hee Lee to lead foundry packaging reinforces that lithography, memory integration, and advanced packaging are now tightly linked. - The EUVL and Source Workshop framed the longer roadmap around High-NA, hyper-NA, sources, materials, metrology, k1 reduction, and sub-13.5-nanometer lithography. Glossary: Extreme Ultraviolet (EUV) lithography — Lithography using 13.5-nanometer light to pattern advanced semiconductor layers. High Numerical Aperture (High-NA) EUV — ASML’s next EUV generation with higher optical numerical aperture for finer patterning. Contacted poly pitch (CPP) — A transistor scaling metric combining gate and source/drain contact dimensions. Two-dimensional transition metal dichalcogenides (2D TMDs) — Atomically thin channel materials such as MoS2, WS2, and WSe2. nFET and pFET — Negative-type and positive-type field-effect transistors used together in CMOS logic. Risk production — Early manufacturing phase used to validate process maturity before full high-volume ramp. High Bandwidth Memory 4E (HBM4E) — A next-generation stacked DRAM technology aimed at high-throughput AI systems. Complementary Field-Effect Transistor (CFET) — A vertically stacked transistor architecture that may extend logic scaling beyond gate-all-around devices.
S1 · E46
June 15 · 16 min
[046] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode treats EUV capacity as a system problem rather than a scanner-count problem. The main thread runs from Rapidus funding and TeraFab signaling to ASML’s policy stance and new research on source efficiency. Key takeaways: - Rapidus completed an additional 150 billion yen government-backed funding round, bringing stated capital and legal capital surplus to 424.95 billion yen. - Rapidus also signed an MoU with the United Kingdom Semiconductor Centre, adding an international collaboration marker to its 2-nanometer roadmap. - Elon Musk’s TeraFab plan was discussed in connection with ASML’s internal technology conference, but no scanner count, node mix, or production timeline has been disclosed. - ASML’s Christophe Fouquet supported demand-driven European technology policy but warned against excessive Commission steering of strategic projects. - Cadence and Intel Foundry expanded DTCO collaboration for Intel 14A, reinforcing that High-NA readiness depends on design enablement as well as optics. - TSMC’s recent comments underline that AI-driven chip demand is constrained by talent, water, infrastructure, and operational sequencing, not only capex. - New EUV source-efficiency papers point to 2-micron laser-driver concepts and conversion-efficiency gains as a possible future productivity lever. - ASML’s AI-native engineering message links scanner productivity to software, diagnostics, defect detection, and service-time reduction. Glossary: Extreme Ultraviolet (EUV) — 13.5-nanometer lithography used for critical layers in advanced logic and memory. High Numerical Aperture (High-NA) — Next-generation EUV optics with higher resolution but more complex cost, mask, and process integration requirements. Design Technology Co-Optimization (DTCO) — Joint optimization of process technology and chip design rules to improve manufacturability and performance. Process Design Kit (PDK) — Foundry-provided files, models, and rules that let designers build chips for a specific process. Conversion efficiency — The fraction of laser energy converted into usable EUV light in the source. Laser-produced plasma — EUV source method in which laser pulses strike tin to generate 13.5-nanometer radiation. TeraFab — Proposed large-scale semiconductor manufacturing project associated with SpaceX, Tesla, and Intel discussions. IIM — Rapidus’ Innovative Integration for Manufacturing site in Chitose, Hokkaido. Source power — EUV light output available for wafer exposure, a key input to throughput and dose margin.
S1 · E45
June 10 · 25 min
[045] Deep Dive Topic - Decodes imec's new logic innovations
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Episode teaser This episode decodes imec's new logic innovation roadmap and explains why future scaling is no longer just about smaller transistors. We walk through the real physical metrics behind node names, the shift from FinFETs to nanosheets and CFETs, the role of High NA EUV, backside power delivery, CMOS 2.0, and active interposers. The focus is on the engineering trade-offs that make the roadmap technically credible, difficult, and important. Key takeaways - Node names are roadmap labels, not literal feature sizes. - Real scaling is better understood through contacted poly pitch, cell height, and metal pitch. - Gate-all-around nanosheets improve channel control and give designers a new drive-current versus area trade-off. - Forksheets may extend the nanosheet era, while CFETs promise tighter logic density through vertical transistor stacking. - High NA EUV improves imaging resolution but requires a new optical, mechanical, mask, and process ecosystem. - Backside power delivery attacks routing congestion and voltage loss by moving power wiring to the wafer backside. - CMOS 2.0 reframes scaling as a three-dimensional system-partitioning problem. - Active interposers could bring memory, photonics, capacitance, and voltage regulation closer to compute. - The future logic roadmap depends on co-optimizing devices, lithography, interconnect, power, packaging, and design tools. Glossary Contacted poly pitch: A physical spacing metric related to the distance between neighboring transistor gates in a standard logic cell. Cell height: The vertical size of a standard logic cell, often expressed in routing tracks. Reducing it improves density but constrains wiring and power resources. Metal pitch: The center-to-center distance between neighboring metal interconnect wires. It strongly affects wiring density and signal delay. FinFET: A fin-shaped field-effect transistor in which the gate controls multiple sides of a raised silicon channel. Gate-all-around transistor: A transistor architecture where the gate surrounds the channel on all sides for stronger electrostatic control. Nanosheet transistor: A gate-all-around transistor using stacked horizontal sheet-like channels. CFET: Complementary field-effect transistor. A future transistor architecture that vertically stacks n-type and p-type devices to reduce standard-cell footprint. High NA EUV: High numerical aperture extreme ultraviolet lithography. A next-generation EUV platform intended to print smaller features with improved resolution. Backside power delivery: A chip architecture that routes power from the wafer backside rather than through the frontside signal wiring stack. CMOS 2.0: Imec's concept for partitioning a system-on-chip into optimized functional tiers connected by dense 3D interconnects. Source list Always Be Curious, “Decoding imec's new industry roadmap for Logic innovation” — https://alwaysbecurious.substack.com/p/decoding-imecs-new-industry-roadmap
S1 · E44
June 9 · 19 min
[044] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at EUV lithography as a coordination problem rather than a single-tool problem. Korea’s approval reform, TSMC’s High-NA cost caution, SK hynix’s wafer-capacity plan, and Rapidus’s fresh government-backed funding all point to the same theme: the industry is trying to turn scarce exposure capacity into usable output faster. The focus topic connects scanner economics with regulation, memory, bonding, research speed, and system-level workarounds. Key takeaways: - South Korea plans to shorten EUV equipment import inspection and approval from 34 days to as few as nine days. - The Korean reform could cut overseas pressure and leak-test fees by about 5 billion won per EUV tool. - TSMC says it has purchased High-NA EUV tools for R&D but does not currently need them for production because the cost remains high. - SK hynix aims to double wafer capacity over the next five years while still expecting memory bottlenecks to persist into 2030. - Rapidus completed an additional 150 billion yen funding round from Japan’s Information-Technology Promotion Agency. - Intel says its 14A PDK 0.5 is available and that 14A PDK 0.9 is targeted for external customers in October. - Imec and EV Group demonstrated wafer-to-wafer hybrid bonding at a 200-nanometer copper pad pitch with post-bond overlay below 40 nanometers. - The University of Texas at Austin described a tabletop EUV and volumetric 3D patterning approach aimed at speeding research experiments, not replacing production scanners. - No new official ASML scanner shipment or throughput announcement was found this week; the ASML share buyback notice was financial housekeeping rather than a capacity update. Glossary: Extreme Ultraviolet (EUV) — lithography using 13.5-nanometer light to pattern critical layers in advanced chips. High Numerical Aperture (High-NA) EUV — next-generation EUV optics with higher resolution but higher cost and integration complexity. Low Numerical Aperture (Low-NA) EUV — today’s production EUV platform used widely for leading-edge logic and advanced memory. Process Design Kit (PDK) — the design-rule and model package customers need to begin designing chips for a foundry process. High Bandwidth Memory (HBM) — stacked DRAM used near AI processors to provide very high memory bandwidth. Dynamic Random-Access Memory (DRAM) — volatile memory technology used in servers, PCs, phones, and HBM stacks. Hybrid bonding — direct wafer or die bonding that creates dense vertical electrical connections for advanced packaging. Post-bond overlay — alignment accuracy after two wafers or dies are bonded. Cost per good die — the economic metric combining process cost, yield, and productivity for shippable chips.
S1 · E43
May 26 · 17 min
[043] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode follows High-NA EUV as it moves from readiness language toward first product evidence. ASML is pointing to memory and logic products exposed within months, while imec’s quantum-dot qubit device shows how High-NA can matter beyond conventional logic and DRAM. The focus is the manufacturing loop around High-NA: masks, inspection, curvilinear data, and qualification. Key takeaways: - ASML’s CEO said first memory and logic products exposed on High-NA EUV systems should appear within months. - imec presented a quantum-dot qubit device fabricated with High-NA EUV, with barely 6-nanometer gaps between control gates. - The episode treats imec’s quantum result as a manufacturability signal, not a near-term revenue driver. - Semiconductor Engineering’s mask discussion points to inspection, repair, curvilinear qualification, and data flow as key High-NA bottlenecks. - Micron started 1-alpha DRAM manufacturing at its Manassas, Virginia fab, adding U.S. long-lifecycle memory capacity outside the EUV-heavy HBM race. - Samsung’s tentative labor deal reduced immediate strike risk, but a later court challenge kept operational uncertainty alive. - No fresh official TSMC or Rapidus update was found this week that changed the EUV outlook. - The practical High-NA question for 2026 is which product layers produce enough yield, cost, and cycle-time evidence to justify insertion. Glossary: Extreme Ultraviolet (EUV) lithography — A 13.5-nanometer exposure technology used for the most advanced semiconductor patterning layers. High Numerical Aperture (High-NA) EUV — ASML’s next EUV generation using 0.55 NA optics for finer resolution and potentially fewer patterning steps. Low Numerical Aperture (Low-NA) EUV — Today’s 0.33 NA EUV platform, still the main production workhorse at leading fabs. Dynamic random-access memory (DRAM) — Volatile memory used in servers, personal computers, mobile devices, and high-bandwidth memory stacks. High Bandwidth Memory (HBM) — Stacked DRAM used near AI accelerators to deliver very high bandwidth. Curvilinear mask — A photomask using curved rather than strictly rectangular features to improve imaging on difficult patterns. Inverse lithography technology (ILT) — Computational method that derives mask shapes from desired wafer patterns and process behavior. Actinic inspection — Mask inspection using EUV wavelength light to better determine whether a defect will print. Edge placement error — The deviation between intended and printed feature edges, increasingly important at advanced nodes.
S1 · E42
May 19 · 6 min
[042] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode frames EUV through geography, serviceability, and industrial replication rather than a new scanner milestone. Tata Electronics and ASML put India’s first commercial 300-millimeter fab into the lithography conversation, while TSMC’s board authorizations and the MATCH Act dispute show why capacity now depends on facilities, field support, policy, and trusted regional execution. Key takeaways: - Tata Electronics and ASML signed an MoU to support the ramp of Tata’s Dholera 300-millimeter fab in Gujarat. - Tata’s disclosed Dholera portfolio spans 28nm, 40nm, 55nm, 90nm, and 110nm, making the project mainly DUV-centered rather than an EUV-frontier fab. - TSMC approved about US$31.284 billion in capital appropriations for advanced technology capacity and fab/facility systems. - TSMC also approved a capital injection of up to US$20 billion into TSMC Arizona. - Dutch objections to the proposed U.S. MATCH Act make servicing, spares, and extraterritorial export controls a live lithography-capacity issue. - China also criticized the MATCH Act, reinforcing that chip-equipment policy is becoming an operating-risk variable. - TSMC reportedly raised its 2030 global semiconductor market view to about US$1.5 trillion, with AI as the demand engine. - Apple-Intel foundry speculation is treated as background this week because the preliminary deal was already covered and no official node or product scope has changed. - No major new EUV scanner shipment or High-NA insertion datapoint was found this week, so the episode focuses on geographic replication and service infrastructure. Glossary: Extreme Ultraviolet (EUV) lithography — 13.5-nanometer wavelength lithography used for critical layers in leading-edge logic and advanced memory. Deep Ultraviolet (DUV) lithography — Earlier-generation optical lithography still essential for mature nodes and many non-critical layers in advanced flows. High Numerical Aperture (High-NA) EUV — Next-generation EUV platform with higher resolution but different economics, field-size constraints, and integration challenges. 300-millimeter fab — Semiconductor wafer fab using 12-inch wafers, the standard format for high-volume modern chip manufacturing. Memorandum of Understanding (MoU) — A formal cooperation framework that may precede detailed contracts or tool orders. Capital appropriation — Board authorization to allocate capital for capacity, construction, facility systems, or related investments. Field service — Maintenance, parts, calibration, and engineering support needed to keep tools productive after installation. MATCH Act — Proposed U.S. legislation aimed at tightening semiconductor manufacturing equipment controls involving China and allied countries. Tool availability — The share of time a manufacturing tool is operational and usable for production work.
S1 · E41
May 11 · 17 min
[041] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at EUV less as a single-tool story and more as a capacity, customer, and capital-allocation story. Apple’s reported Intel and Samsung outreach, Samsung’s 2nm foundry push, SK Hynix customer-financing talks, and TSMC’s low-NA roadmap strategy all point to the same conclusion: the bottleneck is now economic and geopolitical as much as technical. Key takeaways: - Previous scripts or sources were not available in the workspace, so non-repetition was handled on a best-effort basis. - Reuters relayed a Wall Street Journal report that Apple and Intel reached a preliminary chip-making deal, but Intel and Apple declined comment and the product scope remains unclear. - Reuters also relayed Bloomberg reporting that Apple explored U.S. chipmaking with Intel and Samsung, while Reuters could not independently verify the report. - Samsung reported Q1 2026 consolidated revenue of KRW 133.9 trillion and operating profit of KRW 57.2 trillion. - Samsung said its foundry business plans full utilization of advanced-node lines in Q2 2026, broader 2nm customer engagement, and second-generation 2nm mobile ramp in H2 2026. - Reuters reported that Samsung expects more advanced 2nm logic customers and is reviewing a second Taylor, Texas fab while targeting first Taylor volume production in 2027. - Reuters reported that SK Hynix customers have proposed funding production lines and ASML EUV tools, reflecting extreme tightness in AI-driven memory supply. - TSMC introduced A13, A12, and N2U, with N2U planned for 2028 and A13/A12 planned for 2029, while continuing to extract gains from existing EUV platforms. - ASML reported Q1 2026 net sales of €8.8 billion and updated 2026 net sales guidance to €36 billion–€40 billion. - Apple A20 and C2 modem items remain rumors; they were used only as directional signals for custom-silicon and packaging demand. Glossary: Extreme Ultraviolet (EUV) — lithography using 13.5 nm light to pattern the most critical layers in advanced chips. High Numerical Aperture (High-NA) EUV — ASML’s newer 0.55 NA EUV platform designed for finer resolution and future sub-2nm logic and advanced memory. Low numerical aperture (low-NA) EUV — the 0.33 NA EUV platform widely used for current leading-edge logic and memory production. Hyper-NA — a possible future EUV generation above High-NA, still more of a 2030s feasibility topic than a near-term production tool. 2nm — an advanced process-node class using nanosheet or gate-all-around transistor structures, with naming varying by foundry. Wafer-Level Multi-Chip Module (WMCM) — a packaging approach that integrates components at wafer level before singulation. High-Bandwidth Memory (HBM) — stacked DRAM used beside AI accelerators to provide very high data bandwidth. CoWoS — TSMC’s Chip-on-Wafer-on-Substrate advanced packaging family for large AI and high-performance computing packages. Backside power delivery — a routing approach that moves power delivery to the wafer backside to reduce congestion and improve performance. Foundry — a manufacturer that produces chips designed by external customers.
S1 · E40
May 7 · 20 min
[040] Deep Dive Topic - Advanced Packaging
This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Episode teaser Advanced packaging has become one of the decisive technologies behind EUV-era semiconductors. This episode explains how modern packages connect chiplets, high-bandwidth memory, substrates, and cooling into one working system. It also maps the key players across foundries, integrated device manufacturers, OSATs, memory suppliers, substrates, materials, and equipment. Key takeaways - Advanced packaging is not EUV lithography itself. It is the system-level integration technology that makes EUV-era chips usable in real products. - A package is no longer just protection. In high-end computing, it is an electrical, thermal, mechanical, and architectural platform. - Fan-out packaging redistributes chip connections beyond the die outline using molded reconstituted wafers or panels and copper redistribution layers. - Two point five D packaging places logic and memory side by side on a high-density interposer or bridge to increase bandwidth. - Three D packaging stacks active dies vertically to shorten connections, but it makes heat removal, power delivery, testing, and yield harder. - Hybrid bonding removes conventional solder bumps and enables much denser die-to-die connections through direct copper and dielectric bonding. - High-bandwidth memory is a central driver of advanced packaging demand for AI accelerators. - TSMC, Samsung, and Intel are central high-end platform players; ASE, Amkor, and JCET are major OSAT players. - SK Hynix, Samsung, and Micron matter because advanced memory packaging is tightly linked to AI system performance. - Substrate, material, and equipment suppliers such as Ibiden, Unimicron, Shinko Electric, AT&S, Samsung Electro-Mechanics, Ajinomoto, BESI, EV Group, Applied Materials, Tokyo Electron, and ASMPT form the hidden backbone of the ecosystem. Glossary - EUV: Extreme ultraviolet lithography, a front-end chipmaking method used to print very small features in advanced semiconductor processes. - Advanced packaging: High-density semiconductor assembly and integration methods that connect multiple dies, memory stacks, substrates, and thermal structures. - Chiplet: A smaller functional die designed to be combined with other dies inside one package. - Fan-out packaging: A wafer-level or panel-level method that embeds dies and builds redistribution layers to route connections beyond the original die area. - Interposer: A high-density routing layer between dies and the package substrate, often made from silicon, organic materials, or redistribution-layer structures. - Through-silicon via: A vertical metal connection through silicon that carries signals or power between layers. - Hybrid bonding: A bonding method that joins dielectric surfaces and copper pads directly, enabling very dense vertical interconnects. - HBM: High-bandwidth memory, a stacked memory technology placed close to processors for very wide, fast data movement. - OSAT: Outsourced semiconductor assembly and test provider; a company that packages and tests chips for other semiconductor firms. - ABF substrate: A high-performance build-up substrate technology using Ajinomoto Build-up Film as an insulating material.

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