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Condor Currents · Monday

RoadBlock: Rethinking GPU Tensor Core Microarchitecture for Emerging Microscaling Format Support

## Episode Summary In this episode, we cover: - **RoadBlock: Rethinking GPU Tensor Core Microarchitecture for Emerging Microscaling Format Support** (arXiv) - **BitDecoding-FP4: Native FP4 KV Cache Decoding via Algorithm-System Co-Design** (arXiv) - **AI agent designs a complete RISC-V CPU from a 219-word spec sheet in just 12 hours — comparably simple design required 'many tens of billions of tokens' - Tom's Hardware** (google_riscv) - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv) - **Openchip unveils BER10 RISC-V processor as Europe pursues greater digital sovereignty - New Electronics** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

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## Episode Summary
In this episode, we cover:
- **RoadBlock: Rethinking GPU Tensor Core Microarchitecture for Emerging Microscaling Format Support** (arXiv)
- **BitDecoding-FP4: Native FP4 KV Cache Decoding via Algorithm-System Co-Design** (arXiv)
- **AI agent designs a complete RISC-V CPU from a 219-word spec sheet in just 12 hours — comparably simple design required 'many tens of billions of tokens' - Tom's Hardware** (google_riscv)
- **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv)
- **Openchip unveils BER10 RISC-V processor as Europe pursues greater digital sovereignty - New Electronics** (google_riscv)
---
*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

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