Skip to content
Sign in
Artwork for Condor Currents
Condor Currents · October 8

CHiRP: Control-Flow History Reuse Prediction

## Episode Summary In this episode, we cover: - **CHiRP: Control-Flow History Reuse Prediction** (arXiv) - **SVRF: Efficient Register Storage for Long-Vector Architectures** (arXiv) - **WheatForce: Learning From CPU Architecture Mistakes - Hackaday** (google_arch) - **Efinix Sapphire RV64 SoC – Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs - CNX Software** (google_riscv) - **RISC-V Processor Advances Local Chip Design - Open Source For You** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

0:00Duration unknown
Play in

transcript

No transcript — this publisher did not publish one.

show notes

## Episode Summary
In this episode, we cover:
- **CHiRP: Control-Flow History Reuse Prediction** (arXiv)
- **SVRF: Efficient Register Storage for Long-Vector Architectures** (arXiv)
- **WheatForce: Learning From CPU Architecture Mistakes - Hackaday** (google_arch)
- **Efinix Sapphire RV64 SoC – Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs - CNX Software** (google_riscv)
- **RISC-V Processor Advances Local Chip Design - Open Source For You** (google_riscv)
---
*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

more episodes

All episodes