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Condor Currents · September 30

Bandwidth, Not FLOPS: FFT Kernels, Matrix Units and SAR Imaging on Apple M6

## Episode Summary In this episode, we cover: - **Bandwidth, Not FLOPS: FFT Kernels, Matrix Units and SAR Imaging on Apple M6** (arXiv) - **Improving Indirect Branch Prediction in Interpreters via Hardware/Software Co-Design** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - hackaday.com** (google_arch) - **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - Wccftech** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

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## Episode Summary
In this episode, we cover:
- **Bandwidth, Not FLOPS: FFT Kernels, Matrix Units and SAR Imaging on Apple M6** (arXiv)
- **Improving Indirect Branch Prediction in Interpreters via Hardware/Software Co-Design** (arXiv)
- **Checking In On The ISA Wars And Its Impact On CPU Architectures - hackaday.com** (google_arch)
- **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - Wccftech** (google_riscv)
- **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv)
---
*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

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