Skip to content
Sign in
Artwork for Condor Currents
Condor Currents · August 12

ArchAgent v2: A Case Study with the Data Prefetching Championship

## Episode Summary In this episode, we cover: - **ArchAgent v2: A Case Study with the Data Prefetching Championship** (arXiv) - **The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction** (arXiv) - **Migration Using Context Cache for Multicore RISC‐V Processor - onlinelibrary.wiley.com** (google_riscv) - **Chinese Loongson processors have leaky caches, researchers find** (the_register) - **Spectre rears its ugly head again as researchers show some RISC-V chips are susceptible** (the_register) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

0:00Duration unknown
Play in

transcript

No transcript — this publisher did not publish one.

show notes

## Episode Summary
In this episode, we cover:
- **ArchAgent v2: A Case Study with the Data Prefetching Championship** (arXiv)
- **The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction** (arXiv)
- **Migration Using Context Cache for Multicore RISC‐V Processor - onlinelibrary.wiley.com** (google_riscv)
- **Chinese Loongson processors have leaky caches, researchers find** (the_register)
- **Spectre rears its ugly head again as researchers show some RISC-V chips are susceptible** (the_register)
---
*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

more episodes

All episodes